1. Field of the Invention
The present invention generally relates to digital communication systems employing phase locked loops (PLLs) and, more particularly, to an improved high speed digital phase locked loop (DPLL) which has a fixed bandwidth independent of variations in manufacturing process or environment and which is programmable to allow user control of phase shifting of the retiming clock.
2. Description of the Prior Art
Digital communication systems provide links not only between various digital devices such as computers connected in a network but also in more traditional electronic communications as well. For example, the next generation of cellular telephone systems will be digital, and proposals for an all digital high definition television standard are currently under review. In all applications, it is important to minimize the jitter rate of the received pulses and thereby substantially reduce the bit error rate (BER) of a received digital transmission.
Traditionally, phase locked loops (PLLs) have been used for precise tuning in communications systems. The principles of the PLL have been applied to digital communication systems in the form of a digital phase locked loop (DPLL) manufactured as an integrated circuit (IC) on a silicon substrate. The manufacturing process may introduce subtle variations in DPLL chips. In sequential digital logic design, timing variations do not alter the function of a module. As long as set up and hold times are met, the design is indifferent to propagation delay through the elements. However, performance characteristics of high speed digital phase locked loops (DPLLs) using tapped delay lines are greatly affected by propagation delays. When considering manufacturing and environmental variations, it is not uncommon to observe a three fold variation between best case and worst case propagation delays.
As process variations are encountered for these DPLLs, the performance characteristics change. More specifically, the bandwidth of the loop changes. This can degrade the performance of the device by creating a higher than acceptable bit error rate (BER) in data transmission systems. In the analog domain, these variations are accounted for by using adjustable components, like potentiometers and variable capacitors. With DPLLs, a new technique must be used.
U.S. Pat. No. 4,626,798 to Fried discloses a phase locked loop wherein the frequency of the ring oscillator in the PLL is adjusted by controlling the number of delay elements in the ring. Fried employs analog circuitry for this control and, therefore, his approach is not easily implemented using very large scale integration (VLSI) techniques. A similar approach was taken by Herzog in U.S. Pat. No. 4,052,673. U.S. Pat. Nos. 4,677,648 to Zurfluh and 4,972,444 to Melrose et al. disclose the use of delay lines used in DPLLs. These designs rely on non-return to zero (NRZ) code and have fixed low pass filter elements. For those applications where there is no stringent jitter transfer requirement, the DPLLs of Zurfluh and Melrose et al. are adequate. However, for those applications where jitter transfer must be critically minimized, what is needed is a 100% digital design which is absolutely stable and suitable for VLSI fabrication.